The present disclosure relates to fixation or permanent storage of data in memory cells of semiconductor memory devices.
In semiconductor memory devices using static random access memory (SRAM) memory cells, sense amplifiers are typically used to amplify data read from the memory cells. A replica read circuit is often used as a circuit for generating a timing signal for activation of the sense amplifier. The replica read circuit reads data from a memory cell in which fixed or permanently stored data is previously provided, and at that time, generates a control signal for the sense amplifier.
FIG. 1 is a circuit diagram showing a conventional SRAM memory cell in which internal data is fixed or permanently stored. The memory cell 100 of FIG. 1 includes two inverters 101 and 102 which form a latch. Reference characters PL0 and PL1 indicate PMOS load transistors, reference characters ND0 and ND1 indicate NMOS drive transistors, reference characters NA0 and NA1 indicate NMOS access transistors, a reference character VDD indicates a power supply voltage, and a reference character VSS indicates a ground voltage. Reference characters 103 and 104 indicate memory nodes, a reference character 105 indicates a word line, and reference characters 106a and 106b indicate complementary bit lines. As shown in FIG. 1, conventionally, in order to previously provide fixed or permanently stored data, one (104) of the memory nodes of the memory cell 100 is fixed or connected directly to the ground voltage VSS, for example (see Japanese Patent Publication No. 2002-367377 (FIG. 6)).
However, if the memory node of the memory cell is fixed or connected directly to the power supply, a leakage current increases. For example, if the memory node 104 is fixed or connected directly to the ground voltage VSS as shown in FIG. 1, the power supply voltage VDD and the ground voltage VSS are connected directly to the opposite ends of the PMOS load transistor PL1, so that a large leakage current flows.
Moreover, in recent years, as the size has been reduced and the speed has been increased, the thickness of the gate oxide film of transistors has been decreased, so that the resistance to dielectric breakdown has tended to decrease. Therefore, if the gate electrode of a transistor is connected directly to a power supply, the gate oxide film is easily damaged by electrostatic discharge (ESD).
Therefore, there is, for example, a method of fixing or permanently setting the gate to a predetermined level using an output signal of a fixation-dedicated circuit. However, in recent years, the size of SRAM memory cells has been shrinking, and therefore, it has become difficult to ensure a channel region for providing a new interconnect which is extended into the inside of the cell.
As a result of the size reduction, the memory cell shrunk to the maximum degree for reduction of the area is susceptible to variations. A disturbance of the regularity of the layout would have a significant influence on variations and therefore yield.
In such a situation, it is difficult to fix or permanently store data without fixing or connecting the gate directly to the power supply, providing a new interconnect, or disturbing the layout regularity.